1. Field of the Invention
The present invention relates to a process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to external electrical connection regions lying on one face of the substrate, as well as an encapsulating encasement of resin.
2. Description of the Related Art
In principle, the external electrical connection regions of a semiconductor chip and the chip are placed on each side of a substrate and, on one side of the substrate, the encasement surrounds the chip and the electrical connection means.
In the manufacturing technique currently used, each of the chips attached and connected to a substrate plate is individually encased by placing this plate in a mold which has as many individual cavities as there are chips. The substrate is then cut between each encasement. This solution requires the manufacture, use and storage of as many different molds for injecting the encasement as there are different packages having different sizes of chips and different placements of these chips on a substrate plate. Likewise, it is necessary to have a particular cutting tool assigned to each size of chip and to each size of substrate plate. There is a need for an improved process for making semiconductor packages.